A resampling filter, or a sample rate converter, converts an input sample rate to a different output sample rate. It is a widely used filter structure that appears in a variety of applications including general signal processing, medical imaging, wireless communications, and military applications. One particularly useful type of resampling filter is a fractional rate resampling filter. In this type of resampling filter, the output sample rate is a well-defined fraction, U/D, of the input sample rate, where U and D are integers, typically co-prime.
A common implementation of a resampling filter uses decimation or interpolation, or a combination of both. Decimation (or equivalently downsampling) decreases the number of samples of an input signal by a factor of D by removing D minus 1 out of every D samples. Decimation may therefore result in aliasing unless the input signal is band limited in such a way that it is possible to recover the input signal from the downsampled signal without loss of information. Conversely, interpolation (or equivalently upsampling) increases the number of samples of an input signal by a factor of U by inserting (“interpolating”) U minus 1 samples between adjacent samples.
In conventional fractional rate resampling filters, interpolation is generally performed before decimation to preserve the properties of the input signal spectrum and to protect the input signal from aliasing. For example, a conventional U/D fractional rate resampling filter first upsamples the input signal by an upsampling or interpolation factor, U, and second, downsamples the upsampled signal by a downsampling or decimation factor, D. Conventional fractional rate resampling filters thus need to first raise the input signal sample rate before processing and/or downsampling. However, if the input signal sample rate is too high, such implementations of the conventional form of a fractional rate resampling filter may not be feasible. For instance, an FPGA may receive input data from a high speed Analog to Digital Converter at a rate of 500 MHz. If a 2/5 fractional rate conversion is desired (i.e., U=2 and D=5) and upsampling by a factor of U=2 is performed first, the FPGA will need to process signals at a rate of 1 GHz. Such high rates may not be feasible on some devices. Furthermore, even for moderate input sample rates, a large interpolation factor U may raise the sample rate higher than is feasible on some devices.
An alternative to the interpolation and decimation cascade described above is a Farrow filter. A Farrow filter uses polynomial approximation to replace a conventional resampling filter, such that the approximation is done section by section. Commonly used Farrow filters interpolate neighboring sample points via cubic or parabolic interpolation. However, if the application has a strict requirement on the filter response, approximations, and therefore a Farrow filter, cannot be used. Furthermore, if the input sample rate exceeds the device clock rate, a Farrow filter cannot be used either.